The present invention is directed to solid state memory devices, and more particularly to timing control in synchronous memory data transfer.
Solid-state memory exists in various forms, in which data is stored in the form of digital signals, typically semiconductor devices. Flash memory is a non-volatile solid-state memory that can be electronically erased and reprogrammed. Flash memory exists in NAND and NOR types. Dynamic random access memory (DRAM) and static random access memory (SRAM) are volatile memory in which data can be written and read. In these and other forms of memory, transfers of data between the memory and a data transfer port, that is to say programming or writing data into and reading data from the memory, may be performed synchronously. In synchronous data transfer, a timing signal usually referred to as a clock or strobe signal is provided by the system to which the memory is coupled. The system includes an interface between the memory and the data transfer port that controls the timing of the data transfers relative to the timing signal.
Data transfer in blocks increases the speed of the transfers and enables block erase operations in NAND flash memory, for example. The timing of the data transfers may be critical, especially at high bandwidth (data transfer speeds). The window for the transitions in the data signals is small at high bandwidth, and transitions falling outside the window can lead to missed data transfers and corruption of the transferred data. Thus, it would be advantageous if the memory interface included a programmable delay module that provides a defined delay between transitions in the read or write data signals and transitions in the clock or strobe signals.